This application claims priority to Korean Application No. 2000-39560, filed Jul. 11, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor memory devices, and, more particularly, to semiconductor memory devices that utilize spare memory cells to replace normal memory cells that are defective.
Dynamic random access memory (DRAM) devices typically comprise large arrays of memory cells. A semiconductor memory device is frequently treated as defective if one or more memory cells does not operate properly. As the integration density and the processing rate of semiconductor memory devices increase, the probability of occurrence of a defective cell increases. Accordingly, the yield of a wafer, which determines the manufacturing cost of DRAMs and is represented by the ratio of the number of non-defective chips to the total number of chips manufactured on a single wafer, may decrease. To improve the yield of a wafer for memory devices having a high integration density, methods for correcting defective cells become increasingly important.
To correct defective cells, redundancy technology has been used. Conventional redundancy technology uses a spare (i.e., redundant) memory cell block located near a normal memory cell block. FIG. 1 is a partial block diagram illustrating a conventional semiconductor memory device in which defective cells within a normal memory cell block are replaced using a spare memory cell block. Referring to FIG. 1, a semiconductor memory device 100 includes a memory cell block 110 having a plurality of memory cells in rows and columns. The memory cell block 110 is divided into a normal memory cell block NCB and a spare memory cell block SCB. The semiconductor memory device 100 also includes a normal word line driver 120 for driving a word line connected to cells within the normal memory cell block NCB and a spare word line driver 130 for driving a word line connected to cells within the spare memory cell block SCB.
The normal word line driver 120 is illustrated in FIG. 2. The normal word line driver 120 includes a precharger 210, a selector 220, a normal word line driver enabler 230 and a driver 240. PMOS transistors 211 and 212 are turned on in response to activation of a precharge signal PREB to a logic xe2x80x9clowxe2x80x9d level so that nodes A and B are precharged to the level of a power supply voltage VCC. The precharge signal PREB is activated to a logic xe2x80x9clowxe2x80x9d level before a word line driving operation is performed. The logic xe2x80x9chighxe2x80x9d levels of the nodes A and B pass through the respective inverters of the normal word line driver 240 and then become logic xe2x80x9clowxe2x80x9d levels at normal word lines NWE0 and NWE1. When the normal word lines NWE0 and NWE1 are held at the logic xe2x80x9clowxe2x80x9d level, the rows of memory cells that are connected to NEW0 and NEW1 within the normal memory cell block NCB are inactive.
When a normal word line enable signal FB is activated to a logic xe2x80x9chighxe2x80x9d level, an NMOS transistor 231 in the normal word line driver enabler 230 is turned on and the normal word line driver 120 is enabled. NMOS transistors 221 and 222 within the selector 220 are selectively turned on in response to internal address signals DRAiB and DRAi. The internal address signals DRAiB and DRAi may be generated by an address decoder (not shown) using conventional techniques. When the internal address signal DRAiB is at a logic xe2x80x9chighxe2x80x9d level, the NMOS transistor 221 in the selector 220 is turned on. When this occurs, the signal at node A transitions from a logic xe2x80x9chighxe2x80x9d level to a logic xe2x80x9clowxe2x80x9d level. The logic xe2x80x9clowxe2x80x9d level at node A causes the inverter within the driver 240 to drive the normal word line NWE0 to a logic xe2x80x9chighxe2x80x9d level. The normal word line NWE0 at the logic xe2x80x9chighxe2x80x9d level selects a row of memory cells MC0 within the normal memory cell block NCB of FIG. 1. The timing chart of this operation is illustrated in FIG. 3.
Referring again to FIG. 1, when a selected memory cell MC0 in the normal memory cell block NCB is defective, the memory cell MC0 is replaced by a spare memory cell SC0 in the spare memory cell block SCB. As will be understood by those skilled in the art, the occurrence of a defective memory cell within a normal row of memory cells typically causes the entire row to be replaced by a spare row. To achieve this replacement, operation, the semiconductor memory device 100 is provided with a spare word line driver 130 for selecting a row of spare memory cells SC0. The spare word line driver 130 is shown in FIG. 4.
Referring to FIG. 4, the spare word line driver 130 includes a precharger 410, a selector 420, a spare word line enabler 430 and a driver 440. The spare word line driver 130 also includes a spare word line driver enable signal line precharger 450 and a programmable decoder 460. A PMOS transistor 451 in the spare word line driver enable signal precharger 450 is turned on in response to activation of the precharger signal PREB to a logic xe2x80x9clowxe2x80x9d level. This causes a first spare word line driver enable signal F to become a logic xe2x80x9chighxe2x80x9d level. Here, fuses F1 and F2 within the programmable decoder 460 may be selectively cut when a defective cell within the normal memory cell block NCB has been identified. For example, when the memory cell selected by the internal address signal DRAiB in the normal memory cell block NCB is defective, the fuse F1 in the programmable decoder 460 is cut. Therefore, since the fuse F1 is cut, the spare word line driver enable signal F does not become a logic xe2x80x9clowxe2x80x9d level even if the NMOS transistor 461 is turned on in response to the logic xe2x80x9chighxe2x80x9d level of the internal address signal DRAiB.
Thereafter, when a second spare word line driver enable signal PRAD is activated to a logic xe2x80x9chighxe2x80x9d level, an NMOS transistor 431 in the spare word line driver enabler 430 is turned on. When this occurs, node C is pulled to a logic xe2x80x9clowxe2x80x9d level through the NMOS transistor 421 (turned on in response to an enable signal F having a xe2x80x9chighxe2x80x9d logic level) and the NMOS transistor 431. The logic xe2x80x9clowxe2x80x9d level at the node C passes through the inverter within the driver 440 and thus becomes a logic xe2x80x9chighxe2x80x9d level at a spare word line SWE. The spare word line SWE at the logic xe2x80x9chighxe2x80x9d level selects the spare memory cell SC0 in the spare memory cell block SCB. The row of spare memory cells can replace the row of defective memory cells MC0 in the normal memory cell block NCB.
The operation of such a semiconductor memory device 100 can be verified by testing for defective cells. To reduce test time, a multi row address test method in which a plurality of word lines are sequentially driven and tested in response to a single command has been proposed. However, this test method typically has the following problems which will be described with reference to FIG. 5. For purposes of illustration herein, it is assumed that an internal address used for addressing a defective cell within a normal memory cell block is DRAiB. When an internal address DRAi addressing a non-defective cell is input to a semiconductor memory device during a multi-row address test, a normal word line NWE is enabled, and the first spare word line driver enable signal F transitions from a logic xe2x80x9chighxe2x80x9d level to a logic xe2x80x9clowxe2x80x9d level. This transition of the enable signal F to a logic xe2x80x9clowxe2x80x9d level occurs because the NMOS transistor 462 in the decoder 460 of FIG. 4 is turned on in response to the address signal DRAi. Thereafter, the first spare word line driver enable signal F should become a logic xe2x80x9chighxe2x80x9d level and turn on the selector 420 when the internal address DRAiB addressing a defective cell is input. However, the first spare word line driver enable signal F is maintained at the logic xe2x80x9clowxe2x80x9d level after the address signal DRAi is applied. Accordingly, a spare word line SWE is not enabled when the internal address DRAiB is applied. This limitation associated with the circuit of FIG. 4 reduces the effectiveness of the test method whereby the normal word line NWE and the spare word line SWE are sequentially enabled during the test.
Thus, notwithstanding conventional memory devices and test methods for identifying defective memory cells within the memory devices, there continues to be a need for memory devices that can be tested more efficiently.
Integrated circuit memory device according to embodiments of the present invention improve the efficiency of performing multi-row address testing by enabling the reset of enable signal lines connected to spare word line driver circuits after commencement of the test. According to one embodiment of the present invention, an integrated circuit memory device includes a normal memory cell block, having a normal word line electrically coupled thereto, and a spare memory cell block having a spare word line electrically coupled thereto. A word line driver circuit is also provided. The word line driver circuit has a normal word line driver electrically coupled to the normal word line and a spare word line driver electrically coupled to the spare word line. The spare word line driver comprises a programmable address decoder that generates a spare word line driver enable signal (F) on an enable signal line. The spare word line driver also comprises a spare word line driver enable signal precharger that is electrically coupled to the enable signal line. The spare word line driver enable signal precharger, which is responsive to a multi-row address test signal (MRAD), performs the function of resetting the enable signal line after commencement of the multi-row address test. The spare word line driver enable signal precharger may also be responsive to a row active command signal that is asserted repeatedly during the multi-row address test. The spare word line driver may also comprise a selector switch that is responsive to the spare word line driver enable signal.
According to another embodiment of the present invention, the spare word line driver is electrically coupled to a row of spare memory cells and includes a programmable address decoder that generates a spare word line driver enable signal (F) and is responsive to a plurality of row addresses. A spare word line driver enable signal precharger is also provided that resets the spare word line driver enable signal to a logic level that turns on the selector switch when the memory device is undergoing a multi row address test. The spare word line driver may also include circuitry that resets the selector switch from an off-state to an on-state after performance of an address test on at least one row of normal memory cells within said plurality of rows of normal memory cells.
According to still another embodiment of the present invention, a semiconductor memory device is provided that can undergo an efficient multi row address test, during which a plurality of word lines are sequentially enabled and tested. The semiconductor memory device includes a normal memory cell block and a spare memory cell block. A normal word line driver is also provided for enabling word lines connected to memory cells within the normal memory cell block, and a spare word line driver is provided for enabling word lines connected to spare cells within the spare memory cell block.
The spare word line driver may include a selector for activating the spare word line driver in response to a spare word line enable signal and thus enabling a spare word line, a programmable decoder for generating the spare word line enable signal by selectively cutting a plurality of fuses in response to address signals of a defective cell. A spare word line enable signal precharger for precharging the spare word line enable signal. This precharging operation is performed in response to a multi row address test signal, indicating a multi row address test, and a row active command signal that is generated depending on the address signals, during the test.
In another embodiment, the spare word line driver includes a selector for activating the spare word line driver in response to a spare word line enable signal and thus enabling the spare word line, a programmable decoder for generating the spare word line enable signal by selectively cutting a plurality of fuses in response to address signals of a defective cell, and a spare word line enable signal precharger for precharging the spare word line enable signal in response to the transition of the address signals while a multi row address test signal is in an activated state, during the test.
A method of testing a semiconductor memory device includes the steps of driving a word line connected to a memory cell within a normal memory cell block in response to input address signals and generating a spare word line enable signal by selectively cutting a plurality of fuses within a programmable decoder (with the cut fuses corresponding to defective rows of cells) when the memory cell corresponding to the address signals in the normal memory cell block is a defective cell. A step is also performed to precharge the spare word line enable signal in response to a multi row address test signal indicating the multi row address test and a row active command signal generated depending on the address signals. A spare word line connected to a spare cell in the spare memory cell block in then enabled in response to the spare word line enable signal, with the spare cell replacing the defective cell.